1. Field of the Invention
The present invention relates to a reference voltage circuit capable of outputting, with low current consumption, a voltage that is less liable to change due to a temperature change, and has an extremely low GND terminal reference voltage.
2. Description of the Related Art
FIG. 2 is a circuit diagram for illustrating a related-art reference voltage circuit. The related-art reference voltage circuit includes an NMOS transistor 102, an NMOS transistor 103, a PMOS transistor 106, a PMOS transistor 107, a PMOS transistor 201, a resistor 104, a resistor 202, and an output terminal 108. The NMOS transistor 102 has a gate and a drain connected to each other via the resistor 104, the drain being further connected to a gate of the NMOS transistor 103, the gate being further connected to a drain of the PMOS transistor 106. The NMOS transistor 103 has a drain connected to a drain and a gate of the PMOS transistor 107, a gate of the PMOS transistor 106, and a gate of the PMOS transistor 201, and a source connected to the GND terminal 101. The PMOS transistor 106 has a source connected to a power supply terminal 100. The PMOS transistor 107 has a source connected to the power supply terminal 100. The PMOS transistor 201 has a drain connected to the GND terminal 101 via the resistor 202 and to the output terminal 108, and a source connected to the power supply terminal 100. A positive voltage is supplied to the power supply terminal 100 from a power supply, and a negative voltage is supplied to the GND terminal 101 from the power supply. The NMOS transistor 102 has a threshold voltage higher than a threshold voltage of the NMOS transistor 103, and the resistor 104 has a resistance value higher than a resistance value of the resistor 202.
In the related-art reference voltage circuit having the above-mentioned configuration, a current flowing through the NMOS transistor 103, which has a low threshold voltage, is copied by a current mirror circuit formed of the PMOS transistor 107 and the PMOS transistor 106, and the copied current serves as a drain current of the PMOS transistor 106. The drain current of the PMOS transistor 106 flows through the NMOS transistor 102 having a normal threshold voltage via the resistor 104. Thus, when the NMOS transistor 103 and the NMOS transistor 102 have the same drive capability and both the NMOS transistors perform saturated operation, both the NMOS transistors have the same overdrive voltage. Thus, a voltage corresponding to a difference in threshold voltages between both the NMOS transistors is applied to the resistor 104. The voltage applied to the resistor 104 does not change depending on temperature because changes in threshold voltages of both the NMOS transistors due to a temperature change are approximately the same (for example, see Japanese Patent Application Laid-open No. 2010-152510). A circuit formed of the PMOS transistor 201 and the resistor 202 is an additional circuit configured to output a voltage based on the voltage applied to the resistor 104 to the output terminal 108 by the GND terminal reference. With this additional circuit, a current flowing through the resistor 104 is copied and the copied current serves as a drain current of the PMOS transistor 201, and hence a current having the same value as the current flowing through the resistor 104 flows through the resistor 202. Thus, the resistor 104 and the resistor 202 are formed of the same material, and the resistor 202 is set to have a resistance value that is a fraction of the resistance value of the resistor 104, thereby being capable of outputting a voltage that is a fraction of the voltage applied to the resistor 104, from the output terminal 108 by the GND terminal 101 reference voltage.
Further, a minimum operating voltage of the related-art reference voltage circuit having the above-mentioned configuration is a power supply voltage with which the NMOS transistor 103 or the PMOS transistor 106 can perform the saturated operation. That is, the minimum operating voltage is a higher one of a voltage obtained by adding the overdrive voltage of the NMOS transistor 103 to a voltage obtained by adding an absolute value of a threshold voltage of the PMOS transistor 107 and an overdrive voltage thereof, and a voltage obtained by adding an overdrive voltage of the PMOS transistor 106 to a voltage obtained by adding the threshold voltage of the NMOS transistor 102 and the overdrive voltage thereof. If the overdrive voltages are set to be values small enough to be ignored, the minimum operating voltage can be reduced to a higher one of the absolute value of the threshold voltage of the PMOS transistor 107 and the threshold voltage of the NMOS transistor 102.
As described above, the related-art reference voltage circuit is capable of outputting a voltage that is less liable to change due to a temperature change and operating at low voltage, but has a problem in that the reference voltage circuit requires an additional circuit when outputting a GND terminal reference, resulting in an increase in current consumption due the addition of the circuit.